CMOS Fabrication Process
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Song Zhao, Amitabh Jain
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Abstract
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
Claims4
1-16. (canceled)
A CMOS IC, comprising:
- a substrate;
- an NMOS transistor further comprising an NMOS gate with 50 to 500 MPa tensile stress;
- and
- a PMOS transistor further comprising PSD regions with less than 100 dislocations/cm2 in space charge regions of said PSD regions.
Dependencies are inferred from the claim text.