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US 2010/0133620 A1Published application
Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device
AssigneeGlobalfoundries Inc.
InventorRalf Richter
Life of this patent
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Abstract
In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.
Claims25
A method, comprising:
- forming a first stress-inducing layer above first and second conductive lines formed in a device level of a semiconductor device;
- performing an etch process for removing said first stress-inducing layer from above said second conductive lines while maintaining said first stress-inducing layer above said first conductive lines;
- forming a second stress-inducing layer on said second conductive lines and on said first stress-inducing layer that is maintained above said first conductive lines;
- selectively removing said second stress-inducing layer and material of said first stress-inducing layer from above said first conductive lines;
- and
- forming at least one further stress-inducing layer above said first and second conductive lines, said at least one further stress-inducing layer and said first stress-inducing layer inducing the same type of stress.
3 more elements
A method, comprising:
- forming a first stress-inducing layer above a first transistor and a second transistor located in a speed-critical device region and above a first transistor and a second transistor located in a second device region, said first and second transistors of said speed-critical device region being of opposite conductivity type;
- selectively removing said first stress-inducing layer from above said second transistor of said speed-critical device region and from at least one of said first and second transistors of said second device region;
- forming a second stress-inducing layer above said second device region and above said second transistor of the speed-critical device region and on said first stress-inducing layer formed above said first transistor of said speed-critical device region, said second stress-inducing layer having a different type of internal stress than said first stress-inducing layer;
- removing said second stress-inducing layer from said first stress-inducing layer and at least one of said first and second transistors of said second device region;
- and
- forming a third stress-inducing layer above said second device region and said first and second transistors of said speed-critical device region, said third stress-inducing layer and said first stress-inducing layer having the same type of internal stress.
3 more elements
A semiconductor device, comprising:
- a first device region comprising a first N-channel transistor and a first P-channel transistor;
- a second device region comprising a second N-channel transistor and a second P-channel transistor;
- a first stress-inducing layer formed on said first P-channel transistor;
- a second stress-inducing layer formed on said first N-channel transistor;
- and
- a third stress-inducing layer formed on said first stress-inducing layer and on said second N-channel and P-channel transistors of said second device region.
3 more elements
Dependencies are inferred from the claim text.