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US 2010/0133610 A1Published application
Method of forming an integrated power device and structure
AssigneeSemiconductor Components Industries, LLC
InventorsFrancine Y. Robb, Stephen P. Robb, Prasad Venkatraman, Zia Hossain
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Abstract
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
Claims24
An integrated power device comprising:
- a semiconductor substrate of a first conductivity type having a first surface;
- an epitaxial layer on the first surface of the semiconductor substrate, the epitaxial layer having a second conductivity type that is opposite to the first conductivity type and having a first surface that is opposite to the first surface of the semiconductor substrate;
- a vertical power transistor formed on the first surface of the epitaxial layer, the vertical power transistor having a plurality of trench type gates and a channel region between each trench type gate;
- and
- a first doped region having the first conductivity type and within the epitaxial layer, the first doped region extending laterally to underlie each channel region wherein the first doped region does not extend to the first surface of the epitaxial layer.
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A method of forming an integrated power device comprising:
- providing a semiconductor substrate of a first conductivity type having a surface;
- forming a semiconductor layer on the surface of the semiconductor substrate;
- forming a vertical transistor on a first surface of the semiconductor layer including forming a plurality of trench type gates with a channel region between adjacent trench type gates of the plurality of trench type gates;
- and
- forming a first doped region of the first conductivity type within the semiconductor layer and extending laterally to underlie each channel region of the vertical transistor wherein the first doped region has a peak doping concentration that is greater than a doping concentration of the semiconductor layer.
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An integrated power device comprising:
- a semiconductor substrate of a first conductivity type having a first surface;
- a first epitaxial layer of the first conductivity type on the first surface of the semiconductor substrate, the first epitaxial layer having a first surface that is opposite to the first surface of the semiconductor substrate;
- a second epitaxial layer of a second conductivity type on the first surface of the epitaxial layer, the second epitaxial layer having a first surface that is opposite to the first surface of the epitaxial layer;
- a vertical power transistor formed on the first surface of the second epitaxial layer, the vertical power transistor having a channel region and also having a plurality of trench type gates formed within respective plurality of openings formed to extend from the first surface of the first epitaxial layer into the second epitaxial layer;
- a first doped region having the first conductivity type and within the first epitaxial layer, the first doped region extending to underlie each trench type gate of the plurality of trench type gates wherein the first doped region does not extend to the first surface of the second epitaxial layer;
- and
- a second doped region within the second epitaxial layer forming a body region of the vertical power transistor, a portion of the second doped region extending between each trench type gate of the plurality of trench type gates wherein all of the portion of the second doped region overlies the first doped region and does not extend to touch the semiconductor substrate.
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Dependencies are inferred from the claim text.