Methods of providing electrical isolation and semiconductor structures including same
AssigneeMicron Technology, Inc.
InventorsBrent D. Gilgen, Paul Grisham, Werner Juengling, Richard H. Lane
Life of this patent
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Abstract
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.
Claims22
A semiconductor structure, comprising:
- a plurality of isolation trenches in a substrate, the plurality of isolation trenches substantially filled with a fill material;
- a liner in contact with the fill material in the plurality of isolation trenches;
- and
- a plurality of recessed access device trenches in the substrate, each recessed access device trench of the plurality of recessed access device trenches adjacent to the liner and to an oxide pillar overlying the substrate.
A method of isolating gates in a semiconductor structure, comprising:
- forming a plurality of fins in a substrate, each of the plurality of fins having a hard mask material formed on a top surface thereof;
- forming a sacrificial material over the plurality of fins;
- forming a plurality of first trenches in the substrate, each first trench of the plurality of first trenches separating each fin of the plurality of fins;
- depositing a fill material in the plurality of first trenches;
- removing a portion of the fill material to expose a top surface of the hard mask material;
- removing the sacrificial material to form a plurality of second trenches;
- depositing a gate material in the plurality of second trenches;
- and
- removing a portion of the gate material to expose the top surface of the hard mask material.
A method of isolating gates in a semiconductor structure, comprising:
- forming a plurality of fins in a substrate, each of the plurality of fins having a hard mask material formed on a top surface thereof;
- forming a sacrificial material over the plurality of fins;
- forming a plurality of V-shaped trenches in the substrate;
- removing the sacrificial material from the plurality of fins;
- filling the plurality of V-shaped trenches with a gate oxide;
- and
- forming a gate material over the plurality of fins.
A semiconductor structure, comprising:
- a substrate comprising a plurality of fins and a plurality of V-shaped trenches, each V-shaped trench of the plurality of V-shaped trenches separating each fin of the plurality of fins.
A semiconductor structure, comprising:
- a substrate comprising a plurality of fins and a plurality of V-shaped trenches, the plurality of V-shaped trenches substantially filled with a gate oxide;
- and
- a gate material in contact with sidewalls of the plurality of fins.
Dependencies are inferred from the claim text.