Semiconductor device having dummy power line
OwnerIl-Woo Junginventor
Life of this patent
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Abstract
A semiconductor device includes a plurality of circuit blocks respectively arranged both in a first direction and in a second direction that intersects the first direction. A plurality of signal lines extend in one direction of the first direction and the second direction to correspond to and extend over the circuit blocks arranged in the one direction among the plurality of circuit blocks, the signal lines being spaced apart in the other direction of the first direction and the second direction. A plurality of power lines are arranged over the circuit blocks, each power line extending along at least one of the signal lines in the one direction. A dummy power line is arranged between one of the power lines and a signal line adjacent to the one of the power lines in the other direction.
Claims20
A semiconductor device comprising:
- a plurality of circuit blocks respectively arranged both in a first direction and in a second direction that intersects the first direction;
- a plurality of signal lines extending in one direction of the first direction and the second direction to correspond to and extend over the circuit blocks arranged in the one direction among the plurality of circuit blocks, the signal lines spaced apart in the other direction of the first direction and the second direction;
- a plurality of power lines arranged over the circuit blocks, each power line extending along at least one of the signal lines in the one direction;
- and
- a dummy power line arranged between one of the power lines and a signal line adjacent to the one of the power lines in the other direction.
A semiconductor power line control apparatus comprising:
- a signal line and a power line both extending substantially parallel to each other over a semiconductor circuit block;
- and
- a dummy power line between the signal line and the power line and extending over the semiconductor circuit block substantially parallel to the power line,
- wherein the dummy power line is configured to be devoid of power upon a determination that a current draining particle foreign to the semiconductor circuit block is in contact with both the dummy power line and the signal line.
A memory cell array power line control apparatus comprising:
- a signal line and a power line both extending substantially parallel to each other over at least a pair of adjacent memory cell arrays;
- and
- a dummy power line between the signal line and the power line and extending over at least a pair of adjacent memory cell arrays substantially parallel to the power line,
- wherein the dummy power line is configured to be devoid of power upon a determination that a current draining particle foreign to one of the pair of adjacent memory cell arrays is in contact with both the dummy power line and the signal line.
Dependencies are inferred from the claim text.