Three-dimensional architecture for integration of cmos circuits and nano-material in hybrid digital circuits

A method of fabricating a complementary metal oxide semiconductor (CMOS) molecular (CMOL) stack, the method comprising:

• providing a first interconnect layer over a CMOS device layer of a first substrate, the first interconnect layer comprising interface pins electrically coupled to the CMOS device layer of the first substrate;
• providing a second interconnect layer over a CMOS device layer of a second substrate, the second interconnect layer comprising interface pins electrically coupled to the CMOS device layer of the second substrate;
• disposing a first array of nanowires over the first interconnect layer to electrically connect to the interface pins thereof;
• disposing a second array of nanowires over the second interconnect layer to electrically connect to the interface pins thereof;
• disposing a nanowire junction material over at least one of the first array of nanowires or the second array of nanowires;
• and
• forming a CMOL stack by positioning the first substrate and the second substrate so that the first array of nanowires and the second array of nanowires are in opposing relation across the nanowire junction material, thereby forming nanowire crossbar switches, the nanowire crossbar switches bonding the first interconnect layer and the second interconnect layer together, thereby forming the CMOL stack.