Semiconductor device and method for manufacturing the same
AssigneeElpida Memory, Inc.
InventorHiroyuki Fujimoto
Life of this patent
Estimating the term…
Abstract
The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to b5; and multiple capacitors. Respective center positions 4 of the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.
Claims20
A semiconductor device comprising:
- a plurality of first signal lines arranged in parallel with each other at a first line pitch;
- a plurality of second signal lines arranged in parallel with each other at a second line pitch greater than the first line pitch and intersecting with the first signal lines;
- and
- a plurality of capacitors having a center arranged above the first signal line,
- wherein the respective centers of the plurality of capacitors are displaced by a given distance from an intersection of the first signal line and the second signal line in a direction parallel to the first signal line.
A semiconductor device comprising:
- a plurality of first lines extended to a first direction and arranged in parallel with each other at a line pitch twice a minimum processing size defined by a design rule;
- a plurality of second lines extended to a second direction perpendicular to the first direction and arranged in parallel with each other at a line pitch 4√3 times the minimum processing size and intersecting with the first signal lines in plan view;
- and
- a plurality of storage elements having a center arranged above the first line,
- wherein the respective centers of the plurality of storage elements are displaced in the first direction by 1/√3 times the minimum processing size from an intersection of the first signal line and the second signal line.
A method for manufacturing semiconductor device comprising:
- forming a plurality of first signal lines parallel with each other;
- forming a plurality of second signal lines parallel with each other, intersecting with the first signal lines;
- and
- forming a plurality of capacitors,
- wherein the first signal lines are arranged at a first line pitch, and the second signal lines are arranged at a second line pitch greater than the first line pitch, and
- wherein the capacitor is formed so that the center thereof is arranged above the first signal line and in a position displaced by a given distance from an intersection of the first signal line and the second signal line in a direction of arranging the second signal lines.
Dependencies are inferred from the claim text.