Multilayer wiring substrate and method for manufacturing the same

A method for manufacturing a multilayer wiring substrate which has a laminated structure composed of a plurality of conductor layers and a plurality of resin insulating layers stacked alternately and in which a plurality of surface connection terminals to which terminals of a chip component are to be surface-connected are formed on a main face of the laminated structure, and a plurality of via conductors connected to the plurality of surface connection terminals are formed in the resin insulating layers, the method comprising:

• disposing an etching mask on a copper foil layer, and half-etching portions of the copper foil layer exposed from opening portions of the mask, so as to form recesses;
• forming, in the recesses, a gold diffusion prevention layer for preventing gold from diffusing into the copper foil layer;
• layering a gold layer, a nickel layer, and a copper layer in sequence on the gold diffusion prevention layer, thereby forming the plurality of surface connection terminals;
• forming, after removal of the mask, a resin insulating layer which covers the surface connection terminals;
• forming the via conductors in each of the plurality of resin insulating layers and forming a conductor layer of said plurality of conductor layers on each of the resin insulating layers;
• and
• removing the copper foil layer and the gold diffusion prevention layer after forming the via conductors so that the gold layer of the plurality of surface connection terminals projects from the main face.