Self configuring output stages of precision amplifiers
AssigneeMaxim Integrated Products, Inc.
InventorRichard Edward Boucher
Life of this patent
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AssigneeMaxim Integrated Products, Inc.
InventorRichard Edward Boucher
Estimating the term…
Self configuring output stages of precision amplifiers that remain linear when operating into a load that may have a ground reference below the amplifier ground reference, that maintain full amplifier gain while approaching zero output, and that can provide a zero output even when operating into a load that may have a ground reference below the amplifier ground reference, that has a self configuring output stage operable with either a mid-rail or ground reference below amplifier ground, and which maintain a high output impedance when not selected even when the output is above the amplifier supply voltage, or when not powered, thereby allowing amplifier outputs from un-powered amplifiers or amplifiers operating at lower supply voltages to be connected in common for multiplexing to a common load.
An amplifier output stage for operating from a positive rail and an amplifier ground rail, comprising:
The amplifier output stage of 3 wherein fourth circuitry also includes a second NMOS transistor and a second amplifier, the second NMOS transistor having a source, a drain, a gate and a body, the first NMOS transistor having its gate connected to the output of a second amplifier, the second NMOS transistor having its gate coupled to a second select input, its source and body coupled to the amplifier ground rail and its drain coupled to the pull-down input signal, the second amplifier having a negative input coupled to an output reference voltage, a positive input coupled to the amplifier output voltage and an output coupled to the gate of the first NMOS device.
An amplifier output stage for operating from a positive rail and an amplifier ground rail comprising:
The amplifier output stage of 8 wherein fourth circuitry also includes a second NMOS transistor and a second amplifier, the second NMOS transistor having a source, a drain, a gate and a body, the first NMOS transistor having its gate connected to the output of a second amplifier, the second NMOS transistor having its gate coupled to a second select input, its source and body coupled to the amplifier ground rail, and its drain coupled to the pull-down input signal, the second amplifier having a negative input coupled to an output reference voltage, a positive input coupled to the amplifier output voltage and an output coupled to the gate of the first NMOS device.
Dependencies are inferred from the claim text.