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US 2010/0077371 A1Published application
Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same
AssigneeNEC Electronics Corporation
InventorNaohiro Kobayashi
Life of this patent
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Abstract
A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same.
Claims5
A layout design method of a semiconductor integrated circuit, comprising:
- (A) providing a cell layout including a cell having a gate extending in a first direction and first and second diffusion layers so that said gate is arranged between said first and second diffusion layers, said cell having a first distance between a first boundary of said cell and said first diffusion layer in a second direction perpendicular to the first direction, and a second distance between a second boundary of said cell and said second diffusion layer, said first and second distances being set to a limit value;
- (B) generating a library data of said cell for a placement and routing tool, based on said cell layout;
- and
- (C) recording the library data onto a storage device.
1 more element
Dependencies are inferred from the claim text.