Method for Bounded Transactional Timing Analysis

A method, comprising:

• receiving a netlist representing a design for an integrated circuit to perform physical synthesis upon the design for the integrated circuit;
• selecting a portion of the netlist corresponding to a portion of the design for the integrated circuit to be optimized;
• creating a checkpoint in a transaction history while performing the physical synthesis;
• storing a pre-change timing of a timing window representing the portion of the netlist in the transaction history;
• performing a change to the timing window representing the portion of the netlist;
• and
• storing the change in the transaction history.

A computer program product for bounded transactional timing analysis, the computer program product comprising:

• a tangible computer usable medium having computer usable code tangibly embodied therewith, the computer usable program code comprising:
• computer usable program code configured to receive a netlist representing a design for an integrated circuit to perform physical synthesis upon the design for the integrated circuit;
• computer usable program code configured to select a portion of the netlist corresponding to a portion of the design for the integrated circuit to be optimized;
• computer usable program code configured to evaluate a pre-change timing of a timing window representing the portion of the netlist while performing the physical synthesis;
• and
• computer usable program code configured to perform a change to the timing window representing the portion of the netlist while performing the physical synthesis.

A computer program product for bounded transactional timing analysis, the computer program product comprising:

• a tangible computer usable medium having computer usable code tangibly embodied therewith, the computer usable program code comprising:
• computer usable program code configured to receive a netlist representing a design for an integrated circuit to perform physical synthesis upon the design for the integrated circuit;
• computer usable program code configured to select a portion of the netlist corresponding to a portion of the design for the integrated circuit to be optimized;
• computer usable program code configured to create a checkpoint in a transaction history while performing the physical synthesis;
• computer usable program code configured to store a pre-change timing of a timing window representing the portion of the netlist in the transaction history;
• computer usable program code configured to perform a change to the timing window representing the portion of the netlist;
• and
• computer usable program code configured to store the change in the transaction history.