Layout evaluation apparatus and method

A layout evaluation method of evaluating a circuit layout of a semiconductor integrated circuit to be manufactured by estimating a result of planarization in manufacturing the semiconductor integrated circuit, the layout evaluation method comprising:

• dividing the circuit layout into partial areas;
• calculating, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data;
• setting a range of the wiring density, a range of the total perimeter length, and a range of the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on a flatness estimation equation corresponding to a type of the circuit layout;
• and
• generating a map by plotting the critical regions and the partial area data on the same map.

A computer readable storage medium containing instructions that, when executed by a computer, cause the computer to perform a layout evaluation method of evaluating a circuit layout of a semiconductor integrated circuit to be manufactured by estimating a result of planarization in manufacturing the semiconductor integrated circuit, the layout evaluation method comprising:

• dividing the circuit layout into partial areas;
• calculating, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data;
• setting a range of the wiring density, a range of the total perimeter length, and a range of the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on a flatness estimation equation corresponding to a type of the circuit layout;
• and
• generating a map by plotting the critical regions and the partial area data on the same map.