Method and apparatus for word-level netlist reduction and verification using same
AssigneeSynopsys, Inc.
InventorPer M. Bjesse
Life of this patent
Estimating the term…
Abstract
A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.
Claims28
A method for processing a computer implemented representation of a circuit design, comprising:
- representing the sequential circuit design in a machine readable medium, as a data structure defining a netlist as a plurality of nodes, and identifying a first set of nodes that includes word-level datapath nodes in the data structure;
- segmenting the first set of nodes in the data structure into segmented nodes having segment widths corresponding to uniformly treated segments of the corresponding words;
- finding reduced safe sizes for the segmented nodes;
- and
- generating an updated data structure representing the circuit design, using the reduced safe sizes of the segmented nodes.
A data processing system adapted to process a computer implemented representation of a circuit design, comprising:
- a data processor and memory coupled to the data processor, the memory storing instructions executable by the data processor
- to represent the circuit design in the memory as a data structure defining a netlist as a plurality of nodes;
- to identify a first set of nodes that includes word-level datapath nodes in the data structure;
- to segment the first set of nodes in the data structure into segmented nodes having segment widths corresponding to uniformly treated segments of the corresponding words;
- to find reduced safe sizes for the segmented nodes;
- and
- to generate an updated data structure representing the circuit design, using the reduced safe sizes of the segmented nodes.
An article of manufacture providing software adapted to process a computer implemented representation of a circuit design, comprising:
- a memory readable by a data processor, the memory storing instructions executable by the data processor
- to represent the circuit design in the memory as a data structure defining a netlist as a plurality of nodes;
- to identify a first set of nodes that includes word-level datapath nodes in the data structure;
- to segment the first set of nodes in the data structure into segmented nodes having segment widths corresponding to uniformly treated segments of the corresponding words;
- to find reduced safe sizes for the segmented nodes;
- and
- to generate an updated data structure representing the circuit design, using the reduced safe sizes of the segmented nodes.
Dependencies are inferred from the claim text.