Reduced signaling interface method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
Claims1
TAP domain selection circuitry, comprising:
- A. a TAP interface including a test data in lead;
- and
- B. instruction circuitry including:
- i. serial register circuitry with a test data input connected to the test data in lead, an instruction clock input, parallel received instruction outputs, and a reset input, the serial register circuitry being reset to a known state upon receiving an active signal on the reset input;
- ii. decode circuitry having parallel received instruction inputs connected to the parallel received instruction outputs, and parallel decode outputs;
- and
- iii. update register circuitry having parallel inputs connected to the parallel decode outputs, instruction outputs, an instruction update input, and a reset input, the update register circuitry being reset to a known state upon receiving an active signal on the reset input.
Dependencies are inferred from the claim text.