Cryptographic processing device and method for adapting to shared-cache attacks
AssigneeIntel Corporation
InventorDavid Walter Young
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Abstract
Embodiments of a cryptograph processing device and method for adapting to shared-cache attacks are generally described herein. Other embodiments may be described and claimed. In some embodiments, the cryptographic processing device comprises first and second processing units, and a cache that is shared by the first and second processing units. The first processing unit may monitor a number of cache misses that occur during the performance of a first cryptographic process and may switch to performing a second cryptographic process after the number of cache misses exceeds a threshold.
Claims3
A method for operating a cryptographic processing device comprising:
- monitoring a number of cache misses that occur during the performance of a first cryptographic process;
- and
- performing a second cryptographic process after the number of cache misses exceeds a threshold.
A cryptographic processing device comprising:
- first and second processing units;
- and
- a cache shared by the first and second processing units,
- the first processing unit to monitor a number of cache misses that occur during the performance of a first cryptographic process in the first processing unit and to switch to performing a second cryptographic process by the first processing unit after the number of cache misses exceeds a threshold.
A computer-readable medium that stores instructions for execution by two or more processors of a cryptographic processing device, the instructions to configure the device to:
- monitor a number of cache misses that occur during the performance of a first cryptographic process;
- and
- perform a second cryptographic process after the number of cache misses exceeds a threshold.
Dependencies are inferred from the claim text.