Multi master dram architecture

A method for accessing a memory device by a first controller of a plurality of controllers of a system, comprising:

• determining, by the first controller, whether a shared command/address (CA) bus coupling the plurality of the controllers to the memory device is available;
• upon determining that the CA bus is available, asserting, by the first controller, an active signal indicating to the plurality of system controllers that the CA bus is unavailable;
• and
• accessing the CA bus to transfer command and address signals to the memory device.

A controller coupled with (a) a first one of a plurality of data ports of a memory device via a data bus, (b) a shared command/address (CA) bus coupling a plurality of controllers to the memory device, and (c) a memory access control bus coupling the controller to each of the plurality of controllers and the memory device, wherein the controller is configured to:

• determinewhether the CA bus is available;
• upon determining that the CA bus is available, assert an active signal on the memory access control bus indicating to the plurality of controllers that the CA bus is unavailable;
• and
• access the CA bus by transferring command and address signals to the memory device via the CA bus.

A system, comprising:

• a plurality of controllers;
• at least one memory device;
• a plurality of data buses, wherein each data bus couples a respective one of the plurality of controllers to a respective data port of the memory device;
• a shared command/address (CA) bus coupling the plurality of controllers to the at least one memory device;
• and
• a memory access control bus coupling each of the plurality of controllers to each other and the memory device,
• wherein each controller is configured to:
• determinewhether the CA bus is available;
• upon determining that the CA bus is available, assert an active signal on the memory access control bus indicating to the plurality of controllers that the CA bus is unavailable;
• and
• access the CA bus by transferring command and address signals to the memory device via the CA bus.

A system comprising:

• a plurality of memory controllers;
• and
• at least one memory package comprising a plurality of memory devices,
• wherein each of the plurality of memory controllers is configured to access a respective one of the plurality of memory devices in the package, each memory controller being coupled with the memory package via a respective data bus.