Hardware triggered data cache line pre-allocation

A method for improving processor performance, comprising:

• inspecting a memory address of a store operation by a processor to a data cache;
• looking for a cache line already allocated within said data cache for said memory address plus a STRIDE value;
• making a pre-allocation request for said cache line if not already pre-allocated;
• accumulating and scheduling pre-allocation requests with a pre-allocation request stack.
• testing whether said memory address of said store operation by said processor to said data cache is included within a range defined by programmable START and END registers, and if so, then allowing such pre-allocation request;
• using a copy-back buffer to process cache lines that are being evicted from said data cache;
• and
• executing ALLOCATE software commands to inject pre-allocation requests into said pre-allocation request stack;
• wherein, said processor is saved from stall cycles caused when there is a cache miss during a store operation to said data cache.

A means for improving processor performance, comprising:

• means for inspecting a memory address of a store operation by a processor to a data cache;
• means for looking for a cache line already allocated within said data cache for said memory address plus a STRIDE value;
• and
• means for making a pre-allocation request for said cache line if not already pre-allocated;
• wherein, said processor is saved from stall cycles caused when there is a cache miss during a store operation to said data cache.