Advanced processor with cache coherency
AssigneeRMI Corporation
InventorDavid T. HASS
Life of this patent
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Abstract
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
Claims5
An advanced processor, comprising:
- a plurality of processor cores each having a data cache;
- a data switch interconnect coupled with the data cache of each of the plurality of processor cores, in which the data switch interconnect passes memory related information among the plurality of processor cores;
- and
- a level 2 cache coupled to the data switch interconnect which allows sharing of dirty cache lines across the plurality of processor cores, wherein the data switch interconnect includes a ring arrangement with a plurality of ring elements coupled to a respective data cache of the plurality of processor cores and a respective portion of the level 2 cache.
Dependencies are inferred from the claim text.