Instruction cache system, instruction-cache-system control method, and information processing apparatus
AssigneeKabushiki Kaisha Toshiba
InventorSoichiro HOSODA
Life of this patent
Estimating the term…
Abstract
An instruction cache system includes an instruction-cache data storage unit that stores cache data per index, and an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data. The instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.
Claims20
An instruction cache system adopting an n-way set associative system in which an instruction code is cached as cache data, wherein the instruction cache system comprises:
- an instruction-cache data storage unit that stores cache data per index;
- and
- an instruction cache controller that compresses and writes cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data, wherein
- the instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.
An instruction-cache-system control method for controlling an instruction cache system, which adopts an n-way set associative system in which an instruction code is cached as cache data, and comprises an instruction-cache data storage unit that stores cache data per index, wherein the method comprises:
- controlling including compressing and writing cache data in the instruction-cache data storage unit, and controlling a compression ratio of the written cache data, and
- calculating a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.
An information processing apparatus comprising:
- an instruction cache system adopting an n-way set associative system in which an instruction code is cached as cache data;
- and
- a main memory that supplies an instruction code to the instruction cache system, wherein
- the instruction cache system comprises:
- an instruction-cache data storage unit that stores cache data per index;
- and
- an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data, and wherein
- the instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.
Dependencies are inferred from the claim text.