Method and system for parallel execution of memory instructions in an in-order processor
OwnerSebastian C. Winkel, Kalyan Muthukumar +1inventors
InventorsSebastian C. Winkel, Kalyan Muthukumar, Don C. Soltis, JR.
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Abstract
A method of parallel execution of a first and a second instruction in an in-order processor. Embodiments of the invention enable parallel execution of memory instructions that are stalled by cache memory misses. The in-order processor processes cache memory misses of instructions in parallel by overlapping the first cache memory miss with cache memory misses that occur after the first cache memory miss. Memory-level parallelism in the in-order processor can be increased when more parallel and outstanding cache memory misses are generated.
Claims25
A method of parallel execution of a first and a second instruction in an in-order processor comprising:
- determining that the first instruction has a cache memory miss;
- setting an indicator associated with an output operand of the first instruction, wherein the indicator indicates the cache memory miss;
- and
- executing the second instruction responsive to the setting of the indicator notwithstanding the completion of the first instruction.
A compiler to generate object code for an in-order processor comprising:
- a front end to receive source code;
- a Intermediate Representation (IR) block, coupled with the front end, to convert the source code into IR form;
- and
- a code generator, coupled to the IR block to:
- compile the IR into the object code;
- replace an instruction in the object code with a control speculative load instruction, wherein the instruction has a possibility of stalling a first use of an output operand of the instruction when executing in the in-order processor, and wherein the control speculative load instruction is to:
- determine that the instruction has a cache memory miss;
- and
- set an indicator associated with the output operand of the instruction, wherein the indicator indicates the cache memory miss;
- insert a speculation check instruction to determine the indicator setting;
- and
- insert a recovery routine, wherein the recovery routine comprises executing the instruction.
A computer readable medium having instructions stored thereon which, when executed, cause an in-order processor to perform the following method:
- determining that the first instruction has a cache memory miss;
- setting an indicator associated with an output operand of the first instruction, wherein the indicator indicates the cache memory miss;
- and
- executing the second instruction responsive to the setting of the indicator notwithstanding the completion of the first instruction.
Dependencies are inferred from the claim text.