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US 2010/0077140 A1Published application
Scalable schedulers for memory controllers
AssigneeIntel Corporation
InventorsPhilip Abraham, Stanley S. Kulick, Randy B. Osborne
Life of this patent
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Abstract
Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.
Claims20
A memory scheduler comprising:
- a first logic to:
- monitor a first timing parameter corresponding to a portion of a memory device;
- and
- result in a memory request to become a candidate for scheduling to the portion of the memory device in response to satisfaction of the first timing parameter;
- and
- a second logic to:
- monitor a second timing parameter corresponding to rank level of the portion of the memory device;
- and
- result in scheduling of the memory request from the first logic to the portion of the memory device in response to satisfaction of the second timing parameter.
6 more elements
A method comprising:
- determining whether a candidate memory request for scheduling is held by a bank checker logic that owns a bank of a memory device;
- determining whether the candidate memory request is to be preempted by another memory request based on the determination of whether the bank checker logic owns the bank of the memory device;
- and
- issuing one of the candidate memory or the other memory request based on the determination of whether the bank checker logic owns the bank of a memory device.
1 more element
A system comprising:
- a memory device having a plurality of memory cells;
- a processor to access the memory device;
- and
- a memory controller comprising a scheduler, the scheduler comprising:
- a first logic to:
- monitor a first timing parameter corresponding to a portion of the memory device;
- and
- result in a memory request to become a candidate for scheduling to the portion of the memory device in response to satisfaction of the first timing parameter;
- and
- a second logic to:
- monitor a second timing parameter corresponding to rank level of the portion of the memory device;
- and
- result in scheduling of the memory request from the first logic to the portion of the memory device in response to satisfaction of the second timing parameter.
10 more elements
Dependencies are inferred from the claim text.