Flash device and method for improving performance of flash device
AssigneeMediatek Inc.
InventorHong-Ching CHEN
Life of this patent
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Abstract
The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.
Claims23
A flash device, comprising:
- a control integrated circuit (IC), generating a plurality of first access signals with first timings to access a first NAND flash integrated circuit, and generating a plurality of second access signals with second timings to access a second NAND flash integrated circuit, wherein the first timings are different from the second timings;
- the first NAND flash integrated circuit (IC), accessing data stored therein according to the first access signals;
- and
- the second NAND flash integrated circuit (IC), accessing data stored therein according to the second access signals.
A method for improving performance of a flash device, wherein the flash device comprises a control integrated circuit (IC), a first NAND flash integrated circuit (IC), and a second NAND flash integrated circuit (IC), comprising:
- directing the control IC to generate a plurality of first access signals with first timings to access the first NAND flash IC;
- directing the first NAND flash IC to access data stored therein according to the first access signals;
- directing the control IC to generate a plurality of second access signals with second timings to access the second NAND flash IC;
- and
- directing the second NAND flash IC to access data stored therein according to the second access signals,
- wherein the first timings is different from the second timings.
A flash device, comprising:
- a control integrated circuit (IC), generating a plurality of first access signals to access a first NAND flash integrated circuit, and generating a plurality of second access signals to access a second NAND flash integrated circuit;
- the first NAND flash integrated circuit (IC), automatically adjusting first timings of the first access signals to obtain a plurality of first adjusted access signals, and access data stored therein according to the first adjusted access signals;
- and
- the second NAND flash integrated circuit (IC), automatically adjusting second timings of the second access signals to obtain a plurality of second adjusted access signals, and access data stored therein according to the second adjusted access signals.
A flash device, comprising:
- a control integrated circuit (IC), generating a plurality of first access signals with a first current level to access a first NAND flash IC, and generating a plurality of second access signals with a second current level to access a second NAND flash IC, wherein the first current level is different from the second current level;
- the first NAND flash integrated circuit (IC), accessing data stored therein according to the first access signals;
- and
- the second NAND flash integrated circuit (IC), accessing data stored therein according to the second access signals.
Dependencies are inferred from the claim text.