Flash Memory Integrated Circuit with Compression/Decompression CODEC
AssigneeSamsung Electronics Co., Ltd.
InventorJun Young Jeon
Life of this patent
Estimating the term…
Abstract
Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.
Claims17
A flash memory integrated circuit with a compression codec, comprising:
- at least one memory block to include a plurality of pages;
- a compression codec circuit to compress input data;
- and
- a controller circuit to generate a control signal in order to sequentially write the compressed input data in at least one page among the plurality of pages.
A flash memory integrated circuit with a compression codec, comprising:
- at least one memory block to include a plurality of pages;
- a controller circuit to generate a control signal in order to read compressed data that is written in at least one page among the plurality of pages;
- and
- a compression codec circuit to decompress the read compressed data according to a predetermined algorithm,
- wherein the compressed data is written in the at least one page by the compression codec circuit.
A method of operating a flash memory with a compression codec, the method comprising:
- compressing input data of the flash memory according to a predetermined compression algorithm;
- and
- generating a control signal in order to write the compressed input data in at least one page among a plurality of pages that is included in at least one memory block of the flash memory.
A method of operating a flash memory with a compression codec, the method comprising:
- generating a control signal in order to read compressed data that is written in at least one page among a plurality of pages included in at least one memory block of the flash memory;
- and
- decompressing, by a compression codec circuit, the read compressed data according to a predetermined algorithm,
- wherein the compressed data is written in the at least one page by the compression codec circuit.
Dependencies are inferred from the claim text.