Matrix-based scans on parallel processors
AssigneeMicrosoft Corporation
InventorsYuri Dotsenko, Naga Govindaraju, Charles Boyd, John Manferdelli, Peter-Pike Sloan
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AssigneeMicrosoft Corporation
InventorsYuri Dotsenko, Naga Govindaraju, Charles Boyd, John Manferdelli, Peter-Pike Sloan
Estimating the term…
A system and method for performing a scan of an input sequence in a parallel processor having a shared register file. A two dimensional matrix is generated, having a number of rows representing a number of threads and a number of columns based on the input sequence block size and the number of rows. One or more padding columns may be added to the matrix to avoid or reduce memory bank conflicts. A first traversal of the rows performs a reduction or a scan of each of the rows in parallel, storing the reduction values. The reduction values are used during a second traversal to propagate the reduction values. In a segmented scan, propagation is selectively performed based on flags representing segment boundaries.
A parallel processor-implemented method for performing a scan on a parallel processor having a shared register file divided into N memory banks, and a warp size S, based on an operator, of an input sequence having a plurality of elements, the input sequence including a block of length B, comprising:
A system for performing a scan of an input sequence on a parallel processor having a shared register file with N memory banks, comprising a scan kernel configured to perform actions including:
A parallel processor-based system for performing a scan of an input sequence of length B in a parallel processor having a shared register file divided into N memory banks, comprising:
Dependencies are inferred from the claim text.