Recessed Gate Silicon-On-Insulator Floating Body Device With Self-Aligned Lateral Isolation

A method for manufacturing contact areas of a memory array, the method comprising:

• defining an insulative spacer region on opposing sides of a silicon-on-insulator transistor gate;
• and
• creating a lateral isolation trench between two adjacent transistor gates that is self-aligned to the gates, wherein the lateral isolation trench is formed through a non-lithographic process so as to be unconstrained by lithography design rules and that results in the formation of an array of silicon-on-insulator memory cells that are isolated by sub-feature size isolation regions.

A computer-controlled fabrication process executing instructions operable to:

• define an insulative spacer region on opposing sides of a silicon-on-insulator transistor gate;
• and
• create a lateral isolation trench between two adjacent transistor gates that is self-aligned to the gates by forming a plurality of recessed gate devices on a silicon-on-insulator substrate over a buried oxide layer, the recessed gate devices defining the memory array, etching the silicon-on-insulator substrate until the buried oxide layer is reached to form the lateral isolation trench aligned to the gate by the spacer region width, partially filling the lateral isolation trench with a dielectric fill material, filling a remaining portion of the lateral isolation trench with doped polysilicon, and thermally cycling the doped polysilicon to create source and drain regions for each device.