Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking
AssigneeQUALCOMM Incorporated
InventorsShiqun Gu, Thomas R. Toms
Life of this patent
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Abstract
The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
Claims18
A method of aligning die for a stacked IC device, comprising:
- orienting a first plurality of die for a first tier of the stacked IC device such that the first plurality has an axis of symmetry;
- orienting a second plurality of die for a second tier of the stacked IC device such that the second plurality has an axis of symmetry;
- and
- aligning the axis of symmetry of the first plurality to the axis of symmetry of the second plurality to enable stacking of the first and second pluralities of die during manufacturing of the stacked IC device.
A method for improving yield in a stacked IC device manufacturing process, comprising:
- binning into a first bin a first plurality of die for a first tier based on yield of each individual die of the plurality of die;
- and
- binning into a second bin a second plurality of die for a second tier based on yield of each individual die of the second plurality of die, the first plurality yield corresponding to the second plurality yield.
A method of aligning multiple die comprising:
- aligning a first group of die for a first tier of a stacked IC device based on a first alignment point;
- and
- aligning a second group of die for a second tier of the stacked IC device with the first group of die based on the first alignment point.
A stacked IC device manufactured by steps comprising:
- orienting a first plurality of die for a first tier of the stacked IC device such that the first plurality have axes of horizontal and vertical symmetry;
- orienting a second plurality of die for a second tier of the stacked IC device such that the second plurality have axes of horizontal and vertical symmetry;
- and
- aligning the axes of symmetry of the first plurality to the axes of symmetry of the second plurality to enable stacking of the first and second pluralities of die during manufacturing of the stacked IC device.
A method for manufacturing a stacked IC device, comprising:
- pre-aligning a set of donor die groups onto a template block based upon a distance between receiver die groups;
- and
- stacking the set of donor die groups with a plurality of receiver die groups based upon an alignment of a single donor die group of the set and a single receiver die group.
Dependencies are inferred from the claim text.