Systems and methods for a pll-adjusted reference clock
AssigneeHewlett-Packard Development Company, L.P.
InventorJustin Coppin
Life of this patent
Estimating the term…
Abstract
A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.
Claims15
A system, comprising:
- a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal;
- a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal;
- and
- a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input,
- wherein the PLL-adjusted reference clock is used to generate at least one other communication link clock signal.
The system of claim. 2 wherein the serial communication link comprises a root complex.
An electronic device, comprising:
- first and second communication links configured to exchange data;
- and
- a reference clock generator that outputs a reference clock to the first communication link, wherein the first communication link multiplies the reference clock for use as a communication link clock signal and wherein the first communication link divides the communication link clock signal to generate a jitter-matched reference clock for use by the second communication link.
A method, comprising:
- receiving a first reference clock;
- generating a first communication link clock signal by multiplying the first reference clock;
- generating a second reference clock based on the communication link clock signal, the second reference clock follows a jitter pattern of the first communication link clock signal;
- and
- providing the second reference clock to a communication link.
Dependencies are inferred from the claim text.