Jitter control apparatus
AssigneeFujitsu Limited
InventorsYuichiro SAKAMOTO, Hisayuki Ojima
Life of this patent
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Abstract
A jitter control apparatus used in a multiplexing apparatus multiplexing a plurality of signals by asynchronous mapping, includes: a detection unit configured to detect a frequency of timing compensation processes in the asynchronous mapping for each of the plurality of signals; and a selection unit configured to select, on basis of a detection result by the detection unit, a clock signal to be used as a carrier clock for the plurality of signals, from a plurality of clock signals including clock signals extracted from at least one of the plurality of signals.
Claims9
A jitter control apparatus used in a multiplexing apparatus multiplexing a plurality of signals by asynchronous mapping, comprising:
- a detection unit configured to detect a frequency of timing compensation processes in the asynchronous mapping for each of the plurality of signals;
- and
- a selection unit configured to select, on basis of a detection result by the detection unit, a clock signal to be used as a carrier clock for the plurality of signals, from a plurality of clock signals including clock signals extracted from at least one of the plurality of signals.
A multiplexing apparatus multiplexing a plurality of signals by asynchronous mapping, comprising:
- buffer memories, respectively provided for the plurality of signals, configured to store data carried by the plurality of signals;
- a timing compensation unit configured to perform a timing compensation process when a phase error between a writing-in clock extracted from a corresponding signal of the plurality of signals and a reading-out clock for each buffer memory deviates from a predetermined range;
- a detection unit configured to detect a frequency of the timing compensation process for each of the plurality of signals;
- a selection unit configured to select, on basis of a detection result by the detection unit, a clock signal to be used as the reading-out clock, from a plurality of clock signals including clock signals extracted from at least one of the plurality of signals;
- and
- a multiplexer configured to multiplex signals carrying data read out from the buffer memories using the reading-out clock.
A multiplexing apparatus multiplexing a plurality of signals by asynchronous mapping, comprising:
- first buffer memories, respectively provided for the plurality of signals, configured to store data carried by the plurality of signals;
- second buffer memories, respectively provided for the plurality of signals, configured to store data carried by the plurality of signals;
- a first timing compensation unit configured to perform a timing compensation process when a phase error between a writing-in clock extracted from a corresponding signal of the plurality of signals and a reading-out clock for each of the first buffer memories deviates from a predetermined range;
- a second timing compensation unit configured to perform a timing compensation process when a phase error between a writing-in clock extracted from a corresponding signal of the plurality of signals and a reading-out clock for each of the second buffer memories deviates from a predetermined range;
- a detection unit configured to detect a frequency of the timing compensation process by the second timing compensation unit for each of the plurality of signals;
- a selection unit configured to select, on basis of a detection result by the detection unit, a clock signal to be used as the reading-out clock for the first buffer memories, from a plurality of clock signals including clock signals extracted from at least one of the plurality of signals;
- and
- a multiplexer configured to multiplex signals carrying data read out from the first buffer memories using the reading-out clock.
Dependencies are inferred from the claim text.