Test mode signal generator for semiconductor memory and method of generating test mode signals

A test mode signal generator for a semiconductor memory device, comprising:

• a test entry mode setting unit configured to receive a plurality of test entry mode setting addresses in response to a test mode register set signal, and configured to code the test entry mode setting addresses to output a plurality of test entry mode signals;
• a test mode set signal generation unit configured to output a test mode set signal according to the test entry mode signals;
• a test address decoding unit configured to receive a plurality of test mode setting addresses in response to the test mode register set signal, and configured to decode the test mode setting addresses to output a plurality of test address decoding signals;
• a latch unit configured to latch the respective test address decoding signals in response to the test mode set signal to output a plurality of latch signals;
• and
• a test mode signal output unit configured to output a plurality of test mode signals each corresponding to any one of the test entry mode signals, wherein the respective latch signals are controlled by the test entry mode signals to output as the test mode signals.

A method of generating test mode signals for a semiconductor memory, comprising:

• shifting a plurality of test entry mode setting addresses sequentially inputted in response to a test mode register set signal to generate a plurality of shift addresses;
• coding the shift addresses to output a plurality of test entry mode signals;
• outputting a test mode set signal, wherein the test mode set signal is activated when at least one of the test entry mode signals is activated;
• outputting test address decoding signals and latching the test address decoding signals in response to the test mode set signal;
• and
• outputting a plurality of test mode signals each corresponding to any one of the test entry mode signals, wherein the test mode signals are output according to the test entry mode signals and the latched test address decoding signals.

A method of generating test mode signals for a semiconductor memory, comprising:

• receiving a plurality of test entry mode setting addresses, wherein the test entry mode setting addresses are inputted in response to a test mode register set signal;
• outputting a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses;
• latching a plurality of test address decoding signals in response to the test mode set signal;
• and
• outputting a plurality of test mode signals each corresponding to any one of the test entry mode signals, wherein the latched test address decoding signals are controlled by the test entry mode signals to output the test mode signals.