Non-volatile memory device and page buffer circuit thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung-Min Kang, Sangwon Hwang, Jong-Nam Baek
Life of this patent
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Abstract
A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.
Claims19
A non-volatile memory device comprising:
- a cell array including a plurality of memory cells;
- a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state;
- and
- a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.
A non-volatile memory device including a plurality of memory cells, comprising:
- a sensing node connected to a bitline of a selected memory cell;
- a first latch configured to store sensed data from the selected memory cell through the sensing node;
- a second latch configured to store data to be programmed to the selected memory cell;
- an output node for outputting the sensed data of the first latch;
- a ground circuit configured to activate or deactivate a verify-read operation through the sensing node or a column scan operation through the output node with reference to the data to be programmed of the second latch;
- and
- a verify circuit connecting the sensing node to the ground circuit during the verify-read operation and connecting the output node to the ground circuit during the column scan operation.
Dependencies are inferred from the claim text.