Memory device reference cell programming method and apparatus
AssigneeMicron Technology, Inc.
InventorsVishal Sarin, Frankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
Claims29
A method for programming an array of memory cells, comprising:
- programming one or more reference cells of a first logical column of memory cells to a first reference level wherein one or more memory cells of the first logical column are not programmed to the first reference level.
A method for programming reference cells in an array of memory cells logically arranged in rows and columns, comprising:
- programming each column of memory cells such that each reference level of a particular number of reference levels is programmed into at least one reference memory cell of each column of memory cells.
A method for programming reference cells in an array of memory cells, comprising:
- programming a first reference cell of a first row and a first column to a first reference level;
- programming a second reference cell of the first row and a second column to a second reference level wherein the second reference cell is adjacent to the first reference cell by row;
- programming a third reference cell of a second row and a third column to the first reference level;
- and
- programming a fourth reference cell of the second row and a fourth column to the second reference level wherein the fourth reference cell is adjacent to the third reference cell by row;
- wherein the fourth column is adjacent to the third column;
- and
- wherein the third column is adjacent to the second column;
- and
- wherein the second column is adjacent to the first column.
A method for programming reference memory cells in an array of memory cells logically arranged in rows and columns, comprising:
- programming each reference memory cell of a first column to one of a particular number of reference levels;
- and
- programming each reference memory cell of a second column to one of the particular number of reference levels, wherein the first and the second column each comprises an approximately equal number of reference memory cells programmed to each of the particular number of reference levels.
A memory device, comprising:
- an array of memory cells logically arranged in rows and columns;
- and
- control circuitry configured to program one or more reference memory cells of a column of memory cells to a first reference level, wherein one or more memory cells of the first column are not programmed to the first reference level.
A method for programming reference memory cells in an array of memory cells logically arranged in rows and columns, comprising:
- programming each reference memory cell of a first row each to one of a particular number of reference levels;
- and
- programming reference memory cells of a second row each to one of the particular number of reference levels;
- wherein the first and second row each comprise an approximately equal number of reference memory cells programmed to each of the particular number of reference levels;
- and
- wherein adjacent reference cells of each column are programmed to a different reference level.
A method for programming reference memory cells in an array of memory cells logically arranged in rows and columns, comprising:
- programming each reference memory cell of a first column to any of a particular number of reference levels;
- and
- programming each reference memory cell of a second column to any of the particular number of reference levels, wherein the reference cells of the first and the second columns are programmed in a pseudo-random arrangement of reference cells programmed to any of the particular number of reference levels.
Dependencies are inferred from the claim text.