Dynamic erase state in flash device
AssigneeSpansion LLC
InventorAllan Parker
Life of this patent
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AssigneeSpansion LLC
InventorAllan Parker
Estimating the term…
Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell erasure can be performed by changing a voltage state of a single program and erase entity according to the indicated erase direction. By employing the indicator bit with the single program and erase entity decoding scheme, the methods and systems can reduce erase time and/or a number of cycles, thereby increasing system reliability, efficiency, and/or durability.
A method of operating a flash device (100), comprising;
A method of operating a flash device (100), comprising;
A flash device (3100), comprising;
Dependencies are inferred from the claim text.