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US 2010/0073994 A1Published application
Leakage compensation circuit for dynamic random access memory (dram) cells
AssigneeIntel Corporation
InventorsDiaaEldin S. Khalil, Arijit Rayehowdhury, Muhammad M. Khellah, Ali Keshavarzi
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Abstract
A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.
Claims26
A Dynamic Random Access Memory (DRAM) cell comprising:
- a leakage compensation circuit, wherein the leakage compensation circuit allows a compensation current from a source to flow to a memory cell storage node of the DRAM cell to compensate a leakage current from the memory cell storage node of the DRAM cell to improve retention time.
A Dynamic Random Access Memory (DRAM) module comprising:
- a plurality of DRAM cells, wherein each of the plurality of DRAM cells comprises:
- a leakage compensation circuit, wherein the leakage compensation circuit allows a compensation current from a source to flow to a memory cell storage node of the DRAM cell to compensate a leakage current from the memory cell storage node of the DRAM cell to improve retention time.
A system comprising:
- a processor;
- and
- an embedded Dynamic Random Access Memory (DRAM) module coupled with the processor, to execute an instruction of the processor, wherein the embedded DRAM module comprises:
- a plurality of DRAM cells, wherein each of the plurality of DRAM cells comprises:
- a leakage compensation circuit, wherein the leakage compensation circuit allows a compensation current from a source to flow to a memory cell storage node of the DRAM cell to compensate a leakage current from the memory cell storage node of the DRAM cell to improve retention time.
2 more elements
Dependencies are inferred from the claim text.