US 2010/0073992 A1Published application

Semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorYoshihiro UEDA

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to generate a reading voltage and a reference voltage. The generation circuit includes a constant current source connected to a first node, a first replica cell connected between the first node and a second node and fixed to the first resistance state, a second replica cell connected between the second node and a third node and fixed to the second resistance state, a first resistance element connected between the first node and a fourth node, and a second resistance element connected between the fourth node and the third node.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell comprising a first resistance state and a second resistance state based on stored data;
a bit line connected to the memory cell;
a reference cell configured to generate a reference current used to determine the stored data of the memory cell and fixed to the first resistance state;
a reference bit line connected to the reference cell;
and
a generation circuit configured to generate a reading voltage applied to the memory cell and a reference voltage applied to the reference cell,
wherein the generation circuit comprises:
a constant current source connected to a first node;
a first replica cell connected between the first node and a second node and fixed to the first resistance state;
a second replica cell connected between the second node and a third node and fixed to the second resistance state;
a first resistance element connected between the first node and a fourth node;
and
a second resistance element connected between the fourth node and the third node and comprising a resistance substantially the same as a resistance of the first resistance element,
the reading voltage is output from the second node, and
the reference voltage is output from the fourth node.

12 more elements

A semiconductor memory device comprising:

a memory cell comprising a first resistance state and a second resistance state based on stored data;
a bit line connected to the memory cell;
a reference cell configured to generate a reference current used to determine the stored data of the memory cell and fixed to the first resistance state;
a reference bit line connected to the reference cell;
and
a generation circuit configured to generate a reading voltage applied to the memory cell and a reference voltage applied to the reference cell,
wherein the generation circuit comprises:
a constant current source connected to a first node;
a first replica cell connected between the first node and a second node and fixed to the first resistance state;
a second replica cell connected between the second node and a third node and fixed to the second resistance state;
a third replica cell connected between the first node and a fourth node and fixed to one of the first resistance state and the second resistance state;
and
a fourth replica cell connected between the fourth node and the third node and comprising a resistance substantially the same as a resistance of the third replica cell,
the reading voltage is output from the second node, and
the reference voltage is output from the fourth node.

12 more elements

Dependencies are inferred from the claim text.