Techniques For Generating Fractional Clock Signals

A method for generating a clock signal, the method comprising:

• comparing an input clock signal to a feedback clock signal to generate a control signal;
• generating an output clock signal in response to the control signal;
• dividing a frequency of the output clock signal by a first value to generate a first frequency divided signal;
• dividing the frequency of the output clock signal by a second value to generate a second frequency divided signal;
• and
• routing the first and the second frequency divided signals as the feedback clock signal during alternating time intervals.

A locked loop comprising:

• phase detection circuitry that compares an input clock signal to a feedback clock signal to generate a control signal;
• and
• a clock signal generation circuit generating an output clock signal in response to the control signal,
• wherein the locked loop is configured to divide a frequency of the output clock signal by a first value to generate a first frequency divided signal that is routed as the feedback clock signal during a first portion of each period of a select signal, and
• wherein the locked loop is configured to divide the frequency of the output clock signal by a second value to generate a second frequency divided signal that is routed as the feedback clock signal during a second portion of each period of the select signal.