US 2010/0073074 A1 · MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUNCTIONAL BLOCKS

Abstract

A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Claims23

Dependent claims

A microprocessor, comprising:

a first supply node providing a first core voltage;
a functional block having a plurality of power modes, comprising:
a plurality of semiconductor devices, each having a substrate connection;
and
a first substrate bias rail routed within said functional block and coupled to said substrate connection of at least one of said plurality of semiconductor devices;
a first charge node;
first select logic which couples said first substrate bias rail to said first charge node when said functional block is in a low power mode and which clamps said first substrate bias rail to said first supply node when said functional block is in a full power mode;
and
substrate bias logic which charges said first charge node to a first bias voltage at a first offset voltage relative to said first core voltage when said functional block is in said low power mode.

6 more elements

An integrated circuit, comprising:

a substrate;
a functional block comprising a plurality of P-channel devices and a plurality of N-channel devices integrated onto said substrate, each of said plurality of P-channel and N-channel devices comprising a bulk connection, wherein said functional block has an active state and a low power state;
a first bias rail provided on said substrate within said functional block and coupled to said bulk connection of at least one of said plurality of P-channel devices;
a second bias rail provided on said substrate within said functional block and coupled to said bulk connection of at least one of said plurality of N-channel devices;
a first supply conductor provided on said substrate and providing a positive core voltage relative to a reference voltage provided by a second supply conductor provided on said substrate;
and
a substrate bias circuit provided on said substrate having a first output for charging said first bias rail and a second output for charging said second bias rail, wherein said substrate bias circuit asserts said first bias rail to said positive core voltage and asserts said second bias rail to said reference voltage when said functional block is in said active state, and wherein said substrate bias circuit drives said first bias rail to a first bias voltage above said positive core voltage and drives said second bias rail to a second bias voltage below said reference voltage when said functional block is in said low power state.

4 more elements

Dependencies are inferred from the claim text.

Microprocessor with selective substrate biasing for clock-gated functional blocks

Life of this patent

Microprocessor with selective substrate biasing for clock-gated functional blocks

Life of this patent

Abstract

Claims23