Duty control circuit and semiconductor device having the same

A duty control circuit configured to control duty of a clock signal, the duty control circuit comprising:

• a first clock input unit connected to a first node and a second node, the first clock input unit receiving an input clock signal from the first node and transmitting a first signal to the second node in response to the input clock signal;
• a first slew controller connected to the second node and having a plurality of first switches receiving a first voltage level, the plurality of first switches being selectively switched in response to a plurality of first control signals so as to transmit the first voltage level to the second node through the first switches that have been selectively switched, such that a rising slew rate of the first signal at the second node is varied;
• a second clock input unit connected to the second node and a third node, the second clock input unit receiving the first signal from the second node and transmitting a second signal to the third node in response to the first signal of the second node;
• a second slew controller connected to third node and having a plurality of second switches receiving a second voltage level, the plurality of second switches being selectively switched in response to a plurality of second control signals so as to transmit the second voltage level to the third node through the second switches that have been selectively switched, such that a falling slew rate of the second signal at the third node is varied;
• and
• a clock output unit, the clock output unit outputting an output clock signal having a duty that varies in accordance with the rising and falling slew rates of the second signal at the third node.

A semiconductor device having a duty control circuit that controls a duty of a clock signal, the duty control circuit comprising:

• a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal;
• a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied;
• and
• a clock output unit, the clock output unit outputting an output clock signal having a duty that varies in accordance with the slew rate of the signal at the second node.