Clock/data recovery circuit
AssigneeNippon Telegraph and Telephone Corporation
InventorsYusuke Ohtomo, Jun Terada, Kazuyoshi Nishimura, Keiji Kishine
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Abstract
A clock/data recovery circuit includes a data duty correction circuit (400) which outputs corrected data by correcting the duty of input data in accordance with the level of a correction signal, a clock recovery circuit (100) which generates a recovered clock in synchronism with the edge timing of the corrected data, a data decision circuit (200) which performs data decision of the corrected data based on the recovered clock, and a data duty detection circuit (300) which detects the duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to the data duty correction circuit.
Claims14
A clock/data recovery circuit comprising:
- a data duty correction circuit which outputs corrected data by correcting a duty of input data in accordance with a level of a correction signal;
- a clock recovery circuit which generates a recovered clock in synchronism with an edge timing of the corrected data;
- a data decision circuit which performs data decision of the corrected data based on the recovered clock;
- and
- a data duty detection circuit which detects a duty of the corrected data based on the recovered clock and outputs the correction signal representing a duty correction amount to said data duty correction circuit.
Dependencies are inferred from the claim text.