Techniques For Digital Loop Filters
AssigneeAltera Corporation
InventorsWilliam W. Bereza, Mohsen Moussavi, Charles E. Berndt
Life of this patent
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Abstract
A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase adjustment is larger than the first phase adjustment. The second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.
Claims26
A digital loop filter comprising:
- a fine control circuit that adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal;
- and
- a coarse control circuit that adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal, wherein the second phase adjustment is larger than the first phase adjustment, and the second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.
A circuit comprising:
- phase detection circuitry configured to compare a phase of a reference clock signal to a phase of a feedback clock signal to generate first and second phase error signals, wherein the first phase error signal indicates a sign of a phase error between the reference clock signal and the feedback clock signal, and the second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal;
- a fine control circuit that adjusts a phase of the feedback clock signal by first phase adjustments in response to the first phase error signal;
- and
- a coarse control circuit that adjusts the phase of the feedback clock signal by second phase adjustments in response to the second phase error signal, wherein each of the second phase adjustments is larger than each of the first phase adjustments.
A method for adjusting a feedback clock signal, the method comprising:
- generating a first phase error signal that indicates a sign of a phase error between a reference clock signal and a feedback clock signal;
- generating a second phase error signal that indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal;
- adjusting a phase of the feedback clock signal by a first phase adjustment in response to the first phase error signal by adjusting a capacitance at a node;
- and
- adjusting the phase of the feedback clock signal by a second phase adjustment in response to the second phase error signal by adjusting a capacitance at a node, wherein the second phase adjustment is larger than the first phase adjustment.
A digital loop filter comprising:
- a first control circuit that adjusts a phase of a feedback clock signal in response to first and second phase error signals, wherein the first phase error signal indicates when a phase of the feedback clock signal is ahead of a phase of a reference clock signal, and the second phase error signal indicates when the phase of the feedback clock signal is behind the phase of the reference clock signal;
- and
- a second control circuit that adjusts a frequency of the feedback clock signal in response to first and second frequency error signals, wherein the first frequency error signal indicates when a frequency of the feedback clock signal is greater than a frequency of the reference clock signal, and the second frequency error signal indicates when the frequency of the feedback clock signal is less than the frequency of the reference clock signal.
Dependencies are inferred from the claim text.