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US 2010/0073053 A1Published application
Delay locked loop for high speed semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorBeom-Ju Shin
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Abstract
A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.
Claims8
A semiconductor device, comprising:
- a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks;
- an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks;
- and
- an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals,
- wherein a phase of the second DLL clock leads that of the first DLL clock.
2 more elements
Dependencies are inferred from the claim text.