Low jitter large frequency tuning lc pll for multi-speed clocking applications
AssigneePrism Circuits, Inc
InventorsChethan Rao, Alvin Wang, Shaishav Desai
Life of this patent
Estimating the term…
Abstract
ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.
Claims25
A LC-based phase-locked loop circuit, comprising:
- a phase frequency detector for receiving an input signal and a feedback signal and generating an error signal that is proportional to the phase difference of the input signal and the feedback signal;
- a programmable charge pump for modifying the error signal, wherein modifying the error signal includes at least one of increasing or decreasing the voltage level of the signal;
- a programmable loop filter for receiving the modified error signal and removing high frequency components above a predetermined threshold from the error signal, and generating a voltage control signal based on the modified error signal;
- and
- a voltage controlled oscillator having a programmable bias control for generating a signal having a frequency based on the voltage control signal.
The circuit of claim 9, wherein the integer M is at least one of one, two, four, or eight.
A method of auto-calibration for a LC-based phase-locked loop, comprising:
- implementing a first and second counter;
- clocking the first counter with a reference clock signal obtained from a reference clock receiver;
- clocking the second counter with a feedback signal obtained from a voltage controlled oscillator;
- activating all of a set of coarse calibration capacitors in a LC tank circuit at initialization;
- and
- de-selecting one of the coarse calibration capacitors in the set and restarting the counting process if the first counter reaches a first maximum count value prior to the second counter reaching a second maximum count value.
A LC-based phase-locked loop circuit, comprising:
- a phase frequency detector that obtains an input signal and a feedback signal, and generates an error signal that is proportional to the phase difference of the input signal and the feedback signal;
- a charge pump component that increases the voltage of the error signal, wherein the charge pump component includes four charge pumps, and the charge pump component is programmed by activating one or more of the charge pumps;
- a loop filter that obtains the modified error signal, and removes high frequency components above a predetermined threshold from the error signal and generates a voltage control signal based on the modified error signal, wherein the loop filter includes two loop filter resistors and two ripple capacitors, and the loop filter is programmed via activating one or more of at least one of the loop filter resistors or ripple capacitors;
- and
- a voltage controlled oscillator that generates an output frequency based at least in part on the voltage signal, and includes a programmable bias control to facilitate noise reduction.
Dependencies are inferred from the claim text.