Frequency detection circuit and detection method for clock data recovery circuit

A frequency detection circuit, for a clock data recovery (CDR) circuit, comprising:

• a phase detector, adapted for sampling a data signal according to a first clock signal provided by the CDR circuit and obtaining a first plurality of sampling values, and providing a phase instruction signal according to the first plurality of sampling values;
• a first delayer, adapted for delaying the first clock signal so as to obtain a second clock signal;
• a frequency detector, coupled to the first delayer, and adapted for sampling the data signal according to the second clock signal and obtaining a second plurality of sampling values, and providing a frequency instruction signal according to the second plurality of sampling values;
• and
• a logic circuit, coupled to the phase detector and the frequency detector, and adapted to execute a logic computation with the phase instruction signal and the frequency instruction signal to generate a clock instruction signal, wherein the CDR circuit is adapted to adjust a frequency of the first clock signal according to a status of the clock instruction signal.