Synchronizing timing domains based on state variables
AssigneeApple Inc.
InventorWilliam P. Cornelius
Life of this patent
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AssigneeApple Inc.
InventorWilliam P. Cornelius
Estimating the term…
Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This synchronization circuit synchronizes clock signals in different timing domains using state variables. In particular, the synchronization circuit generates a synchronization acquisition curve based on a temporal history of state-variable differences between the clock signals. Next, the synchronization circuit synchronizes the clock signals (without a discontinuous temporal transient in one or more state variables of a dependent one of the clock signals) based on the sum of the synchronization acquisition curve and the state-variable differences between the clock signals. This state variable may include: a phase of the dependent clock signal, a frequency of the dependent clock signal, and/or a rate of change of the frequency of the dependent clock signal.
1 A synchronization circuit, comprising:
The synchronization circuit of claim 1, wherein the sum of the state-variable differences and the synchronization acquisition curve is approximately zero at the beginning of the synchronization of the first clock signal and the second clock signal.
The synchronization circuit of claim 1, wherein the synchronization acquisition curve facilitates synchronizing of the first clock signal and the second clock signal without a discontinuous temporal transient in a state variable of the second clock signal.
The synchronization circuit of claim 1, wherein, at a given time, the temporal history includes a phase difference and a frequency difference between the first clock signal and the second clock signal.
The synchronization circuit of claim 1, wherein the synchronization acquisition curve corresponds to a smooth and continuous function of time of a phase difference between the first clock signal and the second clock signal.
The synchronization circuit of claim 1, wherein, at the beginning of the synchronization of the first clock signal and the second clock signal, the synchronization acquisition curve is based on a phase-difference trajectory as a function of time, which includes a phase difference, a frequency difference, and a rate of change of the frequency difference between the first clock signal and the second clock signal.
The synchronization circuit of claim 1, wherein the synchronization acquisition curve is determined based on a transfer function of a feedback loop between an output of the summation circuit and an input of the comparison circuit, which includes the synchronization processing circuit.
The synchronization circuit of claim 1, wherein the synchronization circuit is disposed on an integrated circuit.
A synchronization circuit, comprising:
An electronic device, comprising a synchronization circuit, wherein the synchronization circuit includes:
A method for synchronizing a first clock signal in a first timing domain and a second clock signal in a second timing domain, comprising:
A computer-program product for use in conjunction with a computer system, the computer-program product comprising a computer-readable storage medium and a computer-program mechanism embedded therein for configuring the computer system for synchronizing a first clock signal in a first timing domain and a second clock signal in a second timing domain, the computer-program mechanism including:
A computer system, comprising:
Dependencies are inferred from the claim text.