Synchronous frequency synthesizer
AssigneeIntel Corporation
InventorsPraveen Dani, Robert Fulton, Andrew M. Volk, Surya Musunuri
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Abstract
An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.
Claims26
An apparatus comprising:
- a phase interpolator, coupled a plurality of input clocks, to receive a first phase setting and to generate a first output with a first phase value within reference phases associated with two input clocks from the plurality of the input clocks;
- a first logic unit to determine a first data including a number of phase steps;
- a divider coupled to the first output to generate an output clock with a first frequency value based on a modifiable divider setting and based on the number of phase steps;
- and
- a second logic unit to determine a plurality of phase settings based on the number of phase steps.
A method comprising:
- determining a first number of phase steps to generate an output clock with a first frequency value;
- determining a final phase setting of a phase interpolator based on the first number of phase steps and a current phase setting of the phase interpolator;
- calculating a second number of phase steps to a reference phase associated with a first input clock of the phase interpolator, wherein the second number of phase steps is less than or equal to the first number of phase steps;
- and
- setting the current phase setting according to the second number of phase steps.
The method of 11, further comprising:
- switching the current phase setting to generate a first output of the phase interpolator from the first input clock only;
- and
- switching the current phase setting to generate the first output of the phase interpolator by interpolating the first input clock and a second input clock.
The method of 11, further comprising:
- calculating a third number of phase steps to reach the final phase setting, and
- setting the current phase setting according to the third number of phase steps.
The method of 11, further comprising determining whether changing the current phase setting to the final phase setting requires crossing one or more reference phases associated with input clocks of the phase interpolator.
The method of 11, further comprising determining a plurality of phase settings associated with one or more reference phases associated with input clocks of the phase interpolator if changing to the final phase setting requires crossing the one or more reference phases.
The method of 11, wherein setting the current phase setting according to the second number of phase steps comprises changing a DAC code of the phase interpolator.
A computer system comprising:
- a processor coupled to an input/output device;
- a clock circuitry coupled to provide a clock signal to the input/output device,
- wherein the clock circuitry comprises:
- a phase interpolator, coupled a plurality of input clocks, to receive a first phase setting and to generate a first output with a first phase value within reference phases associated with two input clocks from the plurality of the input clocks;
- a first logic unit to determine a first data including a number of phase steps;
- a divider coupled to the first output to generate an output clock with a first frequency value based on a modifiable divider setting and based on the number of phase steps;
- and
- a second logic unit to determine a plurality of phase settings based on the number of phase steps.
Dependencies are inferred from the claim text.