Latch structure, frequency divider, and methods for operating same

An electronic latch comprising:

• a means for driving a first output to a first output level when a first input is at a first input level and a second input is at the first input level, driving the first output to a second output level different from the first output level when the first input is at a second input level and the second input is at the second input level, and setting the first output to a high impedance state when different input levels are applied to the first input and to the second input;
• a means for driving a second output to the first output level when a third input is at the first input level and a fourth input is at the first input level, driving the second output to the second output level when the third input is at the second input level and the fourth input is at the second input level, and setting the second output to the high impedance state when different input levels are applied to the third input and to the fourth input;
• and
• a means for maintaining voltage level of the first and second outputs when the means for driving the first output drives the first output to the high impedance state, and the means for driving the second output drives the second output to the high impedance state.

A method of operating an electronic latch, the method comprising:

• driving a first output with a first output logic level in response to a first input and a first clock phase being at a first input logic level;
• driving a second output with the first output logic level in response to a second input and a second clock phase being at the first input logic level;
• driving the first output with a second output logic level in response to the first input and the first clock phase being at a second input logic level;
• driving the second output with the second output logic level in response to the second input and the second clock phase being at the second input logic level;
• providing a high impedance at the first output in response to the first input and the first clock phase being at different input logic levels;
• providing the high impedance at the second output in response to the second input and the second clock phase being at different input logic levels;
• and
• maintaining logic levels of the first and second outputs when the first input and the first clock phase are at different input logic levels, and the second input and the second clock phase are at different input logic levels.