Verification support apparatus, verification support method, and computer product

A verification support apparatus comprising:

• a receiving unit that receives a hardware description of a combinational circuit to be verified;
• a description extracting unit that extracts, from the hardware description, a conditional branch description expressing conditional branch processing;
• an identifying unit that, from among conditional branch descriptions extracted by the description extracting unit and based on a description sequence in the hardware description, identifies a combination of conditional branch descriptions having a hierarchical relation;
• a combination extracting unit that extracts, from among combinations of conditional branch descriptions identified by the identifying unit, a combination having a potential to satisfy a specified condition;
• a creating unit that creates a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted by the combination extracting unit to be satisfied;
• and
• an output unit that outputs, as assertion information of the combinational circuit, the simulation program created for each combination by the creating unit.

A verification support method comprising:

• receiving a hardware description of a combinational circuit to be verified;
• extracting, from the hardware description, a conditional branch description expressing conditional branch processing;
• identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation;
• extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition;
• creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied;
• and
• outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating.