US 2010/0064263 A1 · METHOD FOR COMPACTION OF TIMING EXCEPTION PATHS

Abstract

A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools.

Claims22

Dependent claims

A method for generating a verified circuit design, comprising:

receiving a circuit design specification and one or more criteria associated with said circuit design specification;
generating at least a design netlist and one or more constraints associated with said design netlist based on said received circuit design specification and criteria;
wherein said constraints comprise one or more constraints identifying false paths in said design netlist;
performing a functional analysis to determine if the generated design netlist and constraints meet the received circuit design specification and criteria;
if said generated design netlist and constraints meet the received circuit design specification and criteria in the functional analysis, performing at least one of path compaction and constraint compaction on said generated design netlist and constraints;
performing a timing analysis on the compacted design netlist and constraints to determine if the compacted design netlist and constraints meet the received circuit design specification and criteria;
and
if said generated design netlist and constraints meet the received circuit design specification and criteria in the timing analysis, performing a path optimization on said compacted design netlist to generate a verified circuit design.

5 more elements

Dependencies are inferred from the claim text.

Method for compaction of timing exception paths

Life of this patent

Method for compaction of timing exception paths

Life of this patent

Abstract

Claims22