Error detection schemes for a cache in a data processing system

A cache, comprising:

• a data array for storing a data entry, wherein the data entry is a first part of a same cache line;
• and
• a tag array for storing a tag entry, wherein the tag entry is a second part of said same cache line,
• wherein the tag entry comprises:
• a parity field for storing one or more parity bits associated with a first portion of the tag entry;
• and
• an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry,
• wherein the EDC check bits are used for detecting multiple bit errors, and
• wherein both the parity field and the EDC field are associated with said same cache line.

A method, comprising:

• generating one or more lock parity bits associated with a lock bit;
• generating one or more dirty parity bits associated with a dirty bit;
• generating one or more EDC check bits associated with a plurality of tag address bits and a valid bit;
• storing the one or more lock parity bits and the lock bit within a tag entry of a same single cache line;
• storing the one or more dirty parity bits and the dirty bit within the tag entry of the same single cache line;
• and
• storing the one or more EDC check bits, the plurality of tag address bits, and the valid bit within the tag entry of the same single cache line.

An integrated circuit comprising an instruction cache and a data cache,

• wherein the instruction cache comprises:
• a first tag array for storing first tag address information;
• first parity logic, coupled to the first tag array, the first parity logic using one or more first parity bits to detect a first error in the first tag address information;
• a first cache data array for storing instruction type information;
• and
• first EDC logic, coupled to the first cache data array, the first EDC logic using a first plurality of EDC check bits to detect a second error in the instruction type information;
• and
• wherein the data cache comprises:
• a second tag array for storing second tag address information;
• second EDC logic, coupled to the second tag array, the second EDC logic using a second plurality of EDC check bits to detect a third error in the second tag address information;
• a second cache data array for storing data type information;
• and
• second parity logic, coupled to the second cache data array, the second parity logic using one or more second parity bits to detect a fourth error in the data type information.