US 2010/0064190 A1 · System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits

Abstract

A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.

Claims20

Dependent claims

A system, comprising:

a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain;
wherein the circuit analysis module is further configured to analyze a DUT for sub-circuits within the DUT;
a don't-care analysis module coupled to the circuit analysis module and configured to identify absolute don't-care latches associated with the identified sub-circuits;
wherein the circuit analysis module is further configured to identify a logical description of an identified sub-circuit;
a sub-circuit exception module coupled to the circuit analysis module and configured to select weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit;
and
wherein the sub-circuit exception module is further configured to store the selected weighted input values for the sub-circuit and to associate the selected weighted input values with the logical description.

4 more elements

A computer program product for power reduction during testing, the computer program product comprising:

a computer usable medium having computer useable program code embodied therewith, the computer useable program code comprising:
computer usable program code configured to analyze a device under test (DUT) to identify sub-circuits within the DUT, the DUT comprising a plurality of latches coupled together in a scan chain;
computer usable program code configured to identify absolute don't-care latches associated with the identified sub-circuits;
computer usable program code configured to identify a logical description of an identified sub-circuit;
computer usable program code configured to select weighted input values for the sub-circuit, based on the identified absolute don't-care latches and the logical description;
computer usable program code configured to store the selected weighted input values for the sub-circuit;
and
computer usable program code configured to associate the selected weighted input values with the logical description of the sub-circuit.

5 more elements

Dependencies are inferred from the claim text.

System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits

Life of this patent

System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits

Life of this patent

Abstract

Claims20