US 2010/0064188 A1 · FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS

Abstract

In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

Claims20

Dependent claims

A device comprising:

an enhanced register to provide at least one actuator signal to a memory array, the enhanced register including:
a first memory device including a first enable input, a first data input coupled to a register data input, and a first memory device output, the first memory device output to couple to the memory array, and
a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device provides a first output signal when the first memory device output is to be coupled to the register data input.

A method comprising:

providing a memory device including a first plurality of memory devices and a second plurality of memory devices, the first plurality of memory devices to provide a plurality of actuator signals to a flash memory array, the second plurality of memory devices to store a filter setting for each one of the first plurality of memory devices;
generating at least one data input at a memory controller to be written to the first plurality of memory devices;
filtering the at least one data input based on the filter setting for each one of the first plurality of memory devices to generate a filtered data input;
storing the filtered data input into the first plurality of memory devices;
and
providing the plurality of actuator signals to the flash memory array based on the filtered data input stored in the first plurality of memory devices.

3 more elements

Dependencies are inferred from the claim text.

Filtered register architecture to generate actuator signals

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Filtered register architecture to generate actuator signals

Life of this patent

Abstract

Claims20